1. Technical Field
The present disclosure relates to a master/slave device system capable of automatically assigning addresses to slave devices.
2. Description of Related Art
A typical master/slave device system includes a master device and a plurality of slave devices connected to the master device via a bus, such as RS485 bus, RS442 bus, or other bus types. The master device can communicate with the slave devices via the bus. To enable access thereto, each slave device is assigned a unique address. To communicate with a target slave device, the master device sends the address of the target slave device and a read/write flag, according to which the target slave device can receive or transmit data and reply with a 1-bit acknowledgement. However, in such a master/slave device system, each slave device requires plural I/O pins of the master device for assignment of its address. The number of slave devices in the master/slave device system is limited by the availability of I/O pins therein, limiting expansion of the system.